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Digital Design Verification Engineer
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-03-04
Listing for:
Phizenix
Full Time
position Listed on 2026-03-04
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
- Bachelor's degree in electrical/communications engineering or computer science.
- 3-5+ years of hands-on verification experience, preferably in communication systems.
- Demonstrated success in taking products to high-volume production, ideally achieving first-pass silicon.
- Strong proficiency in System Verilog, UVM, C, and System
C, along with solid scripting expertise. - Excellent problem-solving, debugging, and communication skills (both written and verbal).
- Bachelor's or Master's degree in Electrical/Communications Engineering.
- Experience with verification techniques leveraging analog/mixed-signal reference models.
- Knowledge of coverage-driven verification methodologies and test plan development.
- Familiarity with constrained-random and assertion-based verification techniques.
- Ability to quickly learn and apply new verification methodologies and tools.
- Build and maintain a state-of-the-art verification environment to test RTL against reference analog/mixed-signal models.
- Develop comprehensive verification test plans, create tests, execute regressions, track coverage, and report program progress.
- Collaborate with design and communication systems teams on system-level verification using UVM, System
C, and DPI-C test benches. - Create and manage an automated regression environment to streamline builds and ensure database integrity.
System Verilog, UVM, System
C, DPI-C, C programming, Scripting, Cadence SKILL, EDA tools, IC/ASIC Design & Verification, Data Processing, Electronics, Communication Systems.
California Pay Range
$70-$90 USD
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