Timing Convergence Lead; STA

Shape the Future of Data Centers and Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is obsessed with engineering a brighter future. Every day, we create world-changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Intel is revolutionizing the Data Center and Server segment. Join us and change the way the world builds servers. Intel's Data Center group is seeking talented and enthusiastic designers to join our growing team and take part in developing state-of-the-art servers that will move data at higher speeds in the Data Center, enriching the lives of every person on Earth.

As our Timing Convergence Lead, you'll be at the forefront of cutting‑edge semiconductor design, ensuring our next‑generation server processors meet the most demanding performance requirements. You'll drive timing closure across complex, multi‑domain designs that power the world’s data infrastructure.

• Lead STA Excellence:
  Drive setup, convergence, reviews, and sign-off for multi-mode, multi-corner, multi-voltage domain designs
• Master Timing Closure:
  Perform comprehensive timing analysis and closure at Partition/Sub‑system/FC levels
• Influence & Collaborate:
  Drive convergence by partnering with APR and Design teams as a key stakeholder
• Innovate Methodologies:
  Develop constraint strategies and provide expert feedback on Clock Tree Synthesis (CTS) approaches
• Pioneer ECO Solutions:
  Lead timing ECO implementation strategy development and enable Tweaker/Prime Time ECO flows
• Automate & Optimize:
  Create automation scripts within STA tools for methodology advancement
• Solve Complex Challenges:
  Apply excellent debugging skills to implementation issues with creative, breakthrough solutions
• Evaluate & Advance:
  Assess multiple timing methodologies and tools across various designs and technology nodes

• Deep expertise in digital design implementation (RTL to GDSII) using Synopsys/Cadence tools
• Strong understanding of LVF/POCV variation formats and deep sub‑micron design challenges
• Proven experience with constraint development and cleanup
• Knowledge of advanced CTS strategies and timing optimization techniques

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• 4+ years of experience in Static Timing Analysis (STA)
• Experience in one or more of the following: OCV/POCV/LVF, MMMC, Clock Tree Analysis, and SI/Noise analysis.
• 4+ years of experience with industry‑standard STA tools:
  • Synopsys Prime Time  (preferred) or Cadence Tempus.
  • Experience enabling Tweaker/Prime Timebased ECO flows and closure methodologies on complex multi‑voltage design
• Scripting experience i.e. Tcl, Python, or Perl for automation.
• Experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm)

• Post graduate degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM‑related field
• Server design experience - a significant plus!

• Join a team that’s not just building processors – we’re engineering the future of computing. Your work will directly impact how data centers worldwide operate, making them faster, more efficient, and more powerful. At Intel, your innovations don’t just advance technology; they enrich lives globally.

Ready to do something wonderful? Apply now and help us build tomorrow’s data infrastructure today!

Job Type: Experienced Hire

Shift: Shift 1 (United States of America) Primary

Location:

US, California, Santa Clara Additional Locations: US, Oregon, Hillsboro, US, Texas, Austin Business group:
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