Design Verification Engineer

We are hiring for Analog/Digital
- Physical Design and Verification Engineer opening for one of our Semiconductor clients in Santa Clara, CA (Onsite for 5 days a week) below is the job description, please go through it once and let me know your interest.

Job Title:
Analog Design Engineer

Job Location:
Santa Clara, CA (Onsite for 5 days a week)

Duration: 12 months

Skills : SOC, FPGA, ASIC, Controller, Processor

Minimum Qualifications:

• The ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies
  .
• Hands-on circuit design experience of Ser Des blocks like Equalizers, PLL, Phase-Interpolators, CDR
  , etc. for 28
  
  Gbps+ data rates
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers
• Experience with the design of precision analog circuits like ADC/DACs
• Experience with Mixed signal design/verification flows
• Experience with full-chip designs, ESDs and verification flows
• Excellent oral and written communication skills.

Job Title:
Analog Layout Design Engineer

Job Location:
Santa Clara, CA (Onsite for 5 days a week)

Duration: 12 months

Minimum Qualifications

• The ideal candidate should have a minimum of BS/MS in Electrical Engineering with 8+ years of experience in high-speed/precision analog layout designs in deep sub-micron process technologies (FinFET).
• Experience in industry standard mask design/verification tools (Cadence/Synopsys, Calibre
  )
• Hands-on custom layout design experience of high-speed Ser Des blocks like Equalizers, PLL, Phase-Interpolators, CDR
  , etc.
• Hands-on custom layout design experience of precision analog blocks like ADCs/DACs
• Experience in floor planning, closing design sign-off with multiple rails/ESDs
• Experience in integration of digital hard IPs
• Experience in efficient DRC debugging
  , SKILL coding
• Excellent oral and written communication skills.

Job Title:
Digital Design Engineer

Job Location:
Santa Clara, CA (Onsite for 5 days a week)

Duration: 12 months

Minimum Qualifications

• The ideal candidate should have MS in Electrical Engineering with 8+ years of experience in Ser Des / Micro-controller / High Speed Digital Development.
• Hands on design experience of digital top ICs that include analog/digital hard IPs
  , digital soft IPs and custom design blocks
• Experience with Tensilica Xtensa and ARM microcontrollers
• Experience in designing Ser Des blocks like link training/adaptation/calibration, CDR, DSP based equalizers
• Experience of digital communication protocols like I2C, I3C, SPI, MDIO, UART, JTAG
  , etc.
• Able to actively participate during various phases of the ASIC/SOC design process –Architecture, RTL design, verification, syntheses, P&R and STA.
• Experience with low power design techniques
  , multiple power domain design
  , clock gating
  , multi-VT design
  , DFx, CPF and CDC tools
  .
• Excellent oral and written communication skills
• IP Factory Model

Job Title:
Digital Physical Design Engineer

Job Location:
Santa Clara, CA (Onsite for 5 days a week)

Duration: 12 months

Minimum Qualifications:

• The ideal candidate should have a BS/MS in Electrical Engineering 8+ years of experience in hands on digital physical design in ASIC/SOC products.
• Experience in Industry standard CAD tools (static timing analysis, parasitic extraction, place and route, IR drop analysis, DRC checks)
• Experience in physical design sign-off high-speed digital circuits
• Experience in floor planning, closing design sign-off with multiple rails/ESDs
• Experience in standard cell based high speed digital design environment
• Experience in integration of analog hard-Ips
• Excellent oral and written communication skills

Job Location:
Santa Clara, CA (Onsite for 5 days a week)

Duration: 12 months

Minimum Qualifications

• The ideal candidate should have a BS/MS in Electrical Engineering 8+ years of experience in hands on digital design verification/Mixed signal Co-simulation in ASIC/SOC products.
• Advanced knowledge of HVL methodology UVM/OVM
  , Solid verification skills in problem solving, constrained random testing, and debugging
• Experience in writing scripts in languages such as Perl or Python
• Experience in defining coverage space and writing coverage model a plus
• Experience with System Verilog Assertion SVA a plus
• Familiar with design involving AMBA/APB, AHB, AXI buses
• Familiar with serial interface protocols
  SPI/I2C/I3C/UART/MDIO/JTAG
• Excellent oral and written communication skills.