Analog Engineer

Job Details: Job Description

Are you someone responsible for developing the IP design collateral and managing the IP release, at Intel, you will play a critical role in shaping the development and execution of cutting-edge analog and mixed‑signal circuit designs in advanced process nodes? Your work will directly enable Intel's mission to deliver technology that powers global innovation. You will drive the design, analysis, and optimization of analog circuits, collaborating with multidisciplinary teams to ensure leading performance, reliability, and efficiency.

This is an opportunity to work on impactful designs and solutions that define Intel's competitive edge in the industry, contributing to the creation of products that touch billions of lives.

• Generate and maintain all required design views (Liberty, LEF, GDS, Verilog, etc.)
• Create timing models, power models, and variation models
• Develop and maintain automation scripts for view generation
• Support multiple PDK releases and technology nodes
• Coordinate with design teams for view requirements

• Perform comprehensive QA checks on all deliverable views
• Execute regression testing on generated views
• Validate timing, power, and functional models
• Ensure compliance with foundry and customer requirements
• Maintain QA documentation and test reports

• Develop automation tools to streamline view generation
• Implement quality control processes and methodologies
• Support ISO
  9000 certification requirements
• Collaborate with EDA teams on tool enhancements

• Demonstrated ability to collaborate effectively with cross‑functional teams.
• Ability to develop the front‑end validation environment development, IBIS models, timing using primelib, and BMODs
• Strong problem‑solving skills and ability to deliver under tight timelines.
• Passion for staying abreast of industry trends and applying innovative design techniques.

• Bachelors with 6 years of experience or Master's degree, or 2+ years with a PhD in Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of experience in analog circuit design
• Experience in IP‑collateral generation (timing, front‑end, back‑end, and verification flows) for analog IPs
• Experience with analog behavior modeling, TX/RX block circuit design, and circuit testing.
• Experience with Calibre DRC and similar verification tools.
• Experience in circuit optimization for power, area, and performance.

• IP‑collateral generation (timing, front‑end, back‑end, and verification flows) for GPIOs, High speed IOs and analog IPs.
• Experience with analog behavior modeling(Verilog), TX/RX block circuit design, and circuit testing. QA in Cell level, IP level and Chip level.
• Experience with all design checking rules tools (e.g. Calibre, Synpsys and Candance) and similar verification tools.
• Experience in circuit design and Chip level design.
• Experience in Chip‑level Electronic Design Automation (EDA) tools SoC design flows and requirements.
• QA or validation engineering experience.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America) Primary

Location:

US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state‑of‑the‑art while delighting our customers -- from delivering cutting‑edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments.

Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:
All qualified applicants will receive consideration for…