Lead Debug​/Trace​/Profiling Design Engineer

Job Description

SiFive is seeking a hardware design technical lead who is passionate about designing industry‑leading debug, trace and profiling IP to help drive adoption of RISC‑V as the architecture of choice for SOC designs across a broad range of vertical applications. The role focuses on debug, trace and profiling and is crucial to SiFive’s effort to deliver silicon at the speed of software across its entire IP portfolio, including Essential, Intelligence, Performance, and Automotive product lines.

• Architect, design and implement debug, trace and profiling hardware.
• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators so elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification test benches and tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.

• Knowledgeable in debug, trace and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG, cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience in debugging tools and profiling methods.
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Knowledge of one or more of:
  Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence (a plus).
• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
• MS/PhD in EE, CE, CS or a related technical discipline.

Base Pay Range: $ – $. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The role also comes with a comprehensive benefits package that may include healthcare and retirement plans, paid time off, and more.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. SiFive is an E‑Verify employer and complies with all federal regulations regarding employment eligibility verification.