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Senior Cache Coherency Architect

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: NVIDIA Gruppe
Full Time position
Listed on 2026-05-31
Job specializations:
  • Engineering
    Software Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 152000 USD Yearly USD 152000.00 YEAR
Job Description & How to Apply Below

Job Overview

We are seeking an experienced Senior Cache Coherency Architect to join our ambitious team s opportunity allows you to be part of a world‑class organization that develops scalable, low‑latency, high‑bandwidth coherent interconnect systems. These systems power groundbreaking NVIDIA products such as Grace‑CPU‑Superchip, Grace‑Hopper‑Superchip, and Vera‑Rubin.

Responsibilities
  • Define consistent interconnect architecture, cache‑coherency protocols, and high‑performance on‑chip interconnect interfaces.
  • Contribute to interconnect IP block specifications, build, verification, and integration into the NoC fabric to ensure cache‑coherency compliance.
  • Collaborate with architects to guarantee the interconnect architecture aligns with project power, performance, and area (PPA) requirements.
  • Develop and maintain functional and performance models for the NoC fabric and IP units to assist with analysis and validation.
  • Collaborate with cross‑functional design and verification teams (simulation, emulation, and formal) to ensure implementations align with architectural specifications.
  • Support silicon bring‑up and post‑silicon debug as needed.
Qualifications
  • Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
  • 5+ years of experience in processor design or other high‑performance semiconductor designs.
  • Deep understanding of cache coherency, with hands‑on experience in industry‑standard protocols (e.g., AXI, ACE, CHI).
  • Experience authoring specifications and designing cache‑coherent interconnects.
  • Strong understanding of system and memory subsystem architecture, with a focus on cache‑coherent interconnect.
  • Experience developing coherent IP models (e.g., VIPs, BFMs) for simulation and emulation.
  • Proficiency in C, C++, Python, and Verilog.
Compensation and Benefits

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $152,000

USD–$241,500

USD for Level3, and $184,000

USD–$287,500

USD for Level
4. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until April
24,2026.

NVIDIA is committed to fostering a diverse work environment and is an equal opportunity employer. We do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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Position Requirements
10+ Years work experience
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