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Senior FPGA​/CPLD Logic Architect; RTL, Timing – Equity

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: NVIDIA AI
Full Time position
Listed on 2026-05-31
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 136000 - 218500 USD Yearly USD 136000.00 218500.00 YEAR
Job Description & How to Apply Below
Position: Senior FPGA/CPLD Logic Architect (RTL, Timing) – Equity

NVIDIA AI is seeking a Senior Logic Design Engineer for its DGX FPGA Logic Team in Santa Clara. In this role, you will manage FPGA/CPLD development, focusing on design, verification, and validation activities. Collaborating closely with architecture and validation teams, you will ensure project specifications are met.

The ideal candidate has over 5 years of relevant experience, strong skills in Verilog/System Verilog, and expertise in FPGA EDA tools. This position offers a competitive salary range of $136,000 - $218,500 based on experience.

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Position Requirements
10+ Years work experience
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