Senior Mask Design Engineer

Senior Mask Layout Design Engineer

You will be part of a team responsible for handling complex mixed-signal circuit designs.

• The role entails working collaboratively and multifunctionally with a multidisciplinary team of photonics, CMOS, electronics, and systems engineers.
• Perform physical layout for mixed-signal functions such as PLLs, high‑speed I/O circuits, general I/O, and ESD structure designs in innovative sub‑micron CMOS technologies using Cadence tools.
• Work with ASIC and mixed‑signal engineers to customize designs for integration in VLSI products.
• Perform floor planning, custom layout, and verify against design rules and schematics.
• Handle fill, post‑processing, DRC mitigation, and foundry interactions.

• BS in Electrical Engineering (or equivalent experience).
• At least 6+ years of hands‑on layout design experience.
• Deep understanding of analog circuit layout concepts in sub‑micron CMOS technologies.
• Validated experience with Cadence custom circuit design tools, particularly Virtuoso.
• Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Prime yield.
• Ability to work optimally in a team with strong interpersonal skills and positive energy.
• Proficiency in scripting languages such as Perl, Python, and knowledge of DRC and LVS checking flows.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $132,000 – $207,000 USD for Level4, and $148,000 – $235,750 USD for Level
5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May
31,2026.

NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.