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Senior SOC Verification Engineer; SystemVerilog/UVM
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-06-04
Listing for:
Apple Inc.
Full Time
position Listed on 2026-06-04
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading technology company in Santa Clara is looking for a Design Verification Engineer to ensure the functionality and performance of their SOCs. The role involves developing test plans, collaborating with design teams, and verifying various hardware components. The ideal candidate has a BS degree and at least 10 years of relevant industry experience. This position offers a competitive salary and comprehensive benefits, including stock options and educational reimbursements.
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Position Requirements
10+ Years
work experience
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