Design Test; DFT​/DFx Methodology and Architecture Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The Circuit Technology team is looking for a passionate and experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed Ser Des PHYs
, next-generation Memory PHYs
, and die-to-die interconnect IPs
.

In this role, you will own and drive DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will work closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP.

Be part of a team that delivers industry-leading IP used across AMD SoCs.

The ideal candidate has strong analytical and problem‑solving skills, excellent attention to detail, and the ability to drive complex technical tasks independently. The candidate should be comfortable working hands‑on while also providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug.

We welcome candidates at multiple experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the level listed in this posting.

• Define and lead PHY‑specific DFT/DFx architecture and methodology for high‑speed Ser Des, Memory PHY, and die‑to‑die interconnect IPs.
• Implement DFT/DFx features in RTL using Verilog/System Verilog.
• Develop and support DFT micro‑architecture, including scan architecture, test modes, clocking, reset, isolation, bypass, and observability features.
• Support JTAG/IJTAG, ICL/PDL, scan compression, at‑speed scan, and hierarchical DFT implementation.
• Support Siemens Tessent‑based or equivalent industry‑standard DFT flows for ATPG, pattern generation, pattern validation, and debug.
• Support scan stitching, scan readiness checks, test coverage analysis, and DFT rule/debug closure.
• Develop and maintain DFT timing constraints, test‑mode constraints, and integration guidelines compatible with front‑end and physical design flows.
• Perform gate‑level simulation and debug using tools such as Synopsys VCS and Verdi.
• Drive Spy Glass or equivalent lint/DFT‑readiness analysis to identify scan, cont rollability, observability, and test coverage gaps.
• Plan, implement, and verify MBIST‑related features for embedded memories.
• Support ATPG pattern generation, simulation, debug, and delivery to test engineering.
• Partner with Test Engineering and Product Engineering on silicon bring‑up, tester pattern debug, diagnosis, and yield‑learning activities.
• Develop efficient, reusable DFx flows, scripts, checkers, and methodologies for IP‑level and SoC‑level integration.

• Hands‑on experience with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent Test Kompress, Tessent Memory
  
  BIST, IJTAG, ICL/PDL, and/or Streaming Scan Network/SSN.
• Relevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology. Level will be determined based on experience and interview assessment.
• Strong understanding of DFT architectures and micro‑architectures, including scan, compression, test clocks, test resets, lock‑up latches, clock gates, scan anchors, and test access mechanisms.
• Hands‑on RTL coding experience in Verilog and/or System…