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Process Engineer – Die to Wafer Hybrid Bonding
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-06-05
Listing for:
Applied Materials, Inc.
Full Time
position Listed on 2026-06-05
Job specializations:
-
Engineering
Electrical Engineering, Process Engineer
Job Description & How to Apply Below
** Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT.
If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.
** What We Offer
** Salary:$ - $
Location:
Santa Clara,CAYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more.
At Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our .As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor manufacturing technologies.
You will collect and analyze data, perform hardware characterization, and troubleshoot engineering issues. You'll also measure film properties, generate technical documentation, and engage with customers to resolve concerns. Process Engineers collaborate with vendors and suppliers, and become familiar with implementing new technologies and products. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects.
Join the Photonics Platforms Business Group within the CTO Office at Applied Materials’ Santa Clara headquarters, where you will work with a world‐class research team developing next‐generation optical interconnects technologies.
We are seeking
** hands‐on
** Process Engineers to drive die‐to‐wafer (D2W) hybrid bonding R&D for silicon photonics and co‐packaged optics applications. This role focuses on hybrid bonding process development, pathfinding, technology de‐risking, and integration exploration.
The engineer will develop and evaluate novel bonding flows enabling photonic–electronic co‐integration, a critical enabler for AI and HPC systems. The role provides on‐the‐job training and hands‐on experience with state‐of‐the‐art equipment, including the industry’s first fully integrated die‐to‐wafer hybrid bonding system.
** Key Responsibilities
*** Develop die‐to‐wafer hybrid bonding processes, including (but not limited to): + Surface preparation and plasma activation + High‐accuracy die placement and alignment + Post‐bond characterization and process evaluation
* Integrate D2W bonding with adjacent process modules such as: + Dicing and die preparation + Die thinning + Inter‐die gap fill and planarization
* Design and execute DOE‐driven experiments to understand process limits, sensitivities, and trade‐offs.
* Own process optimization, perform failure analysis and characterization, and drive continuous engineering improvement.
** Qualifications
* ** M.S. or Ph.D. in Materials Science, Electrical Engineering, Applied Physics, or a related STEM discipline.
* In‐depth knowledge and hands‐on experience in one or more of the following: + Die‐to‐wafer or wafer‐to‐wafer bonding + Thin‐die handling and alignment‐critical processes + Direct process engineer experience on mainstream semiconductor equipment (plasma, wet clean, overlay/alignment, etc.) + 2.5D/3D integration
* Strong understanding of: + Bond interface physics + Alignment and overlay fundamentals + Mechanical behavior of thin and fragile dies
* Proficiency in statistical analysis and process control (e.g., DOE, SPC, JMP).
*…
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