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Senior Verification Engineer: SystemVerilog/UVM SoC
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-06-06
Listing for:
iFlow Inc.
Full Time
position Listed on 2026-06-06
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
iFlow Inc. is seeking a Design Verification Engineer based in Santa Clara, CA, for a long-term position. The successful candidate will possess 8-15 years of experience, showcasing a strong proficiency in System Verilog and UVM, alongside debugging skills.
Key responsibilities include developing verification environments for testing, performing coverage analysis, and collaborating with RTL designers to debug simulation failures while ensuring design quality across various domains.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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