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Senior ASIC Modeling Software Engineer

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Upscaleai
Full Time position
Listed on 2026-06-06
Job specializations:
  • Engineering
    Systems Engineer, Software Engineer, AI Engineer (Applied/Software), Hardware Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 180000 USD Yearly USD 150000.00 180000.00 YEAR
Job Description & How to Apply Below

Location: On-site in Santa Clara, CA
Job Type: Full-Time
Company: Upscale AI
Team Size: +100 employees
Industry: High-Tech / Emerging Infrastructure
Department: ASIC AI

Why join Upscale AI

Upscale AI is building high-performance infrastructure powering the next generation of artificial intelligence. Backed by over  300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale AI is where you can produce meaningful work at the frontier—and operate at a high standard.

Position Overview

We’re building the simulation platform for Upscale

AI’s next-generation AI networking ASICs. The platform is a functionally accurate software model of our ASIC architecture, enabling software development, verification, and customer validation before silicon is available. You’ll be responsible for developing, testing and maintaining the platform across multiple ASIC generations, ensuring it accurately represents hardware behavior and scales to support our customers’ demanding AI infrastructure workloads.

Key Responsibilities
  • Design and implement software model components that accurately simulate ASIC behavior (forwarding engines, schedulers, memory subsystems, control plane interfaces)
  • Translate architectural specifications and microarchitecture documents into high-fidelity C++ models, ranging from functionally accurate to performance-accurate depending on the subsystem
  • Develop and maintain the register model, memory map, and configuration interfaces
  • Implement packet processing pipelines for multiple forwarding modes
  • Optimize model performance for large-scale simulations
  • Collaborate with RTL engineers to ensure model-to-silicon correlation
  • Work with the architecture team to validate algorithm and architectural choices through simulation
  • Work with SDK and platform software teams to enable software development and validation on the model
  • Support multiple ASIC versions with maintainable, configurable model architecture
Requirements
  • 7+ years of experience in C/C++ architecture model development, cycle-aware simulation, or ASIC verification
  • Expert-level C++ programming (modern C++17)
  • Deep understanding of network switch/router architecture: forwarding tables, scheduling, QoS, ACLs
  • Experience with packet processing pipelines and dataplane simulation
  • Familiarity with hardware description languages (Verilog/System Verilog) and reading RTL
  • Experience with gRPC, Protocol Buffers, or similar IPC mechanisms
  • Experience with C++ unit testing frameworks (e.g., Google Test)
  • Familiarity with Python for test automation, tooling, and scripting
  • Strong debugging skills across software and hardware domains
Nice to Have
  • Experience with AI/ML networking (scale‑up fabrics, RDMA, collective operations)
  • Experience using ns-3 and/or HTSim to model high performance network architectures.
  • Familiarity with SAI (Switch Abstraction Interface) or SONiC
  • Experience with FPGA prototyping or emulation platforms
  • Background in memory subsystem modeling (DDR, HBM, caches)
  • Experience with configuration-driven simulation frameworks (YAML, JSON, protobuf-based config)
What You’ll Work On
  • ASIC Architectural Model:
    Our current‑generation ASIC simulator
  • Next‑gen ASIC models:
    Future silicon with enhanced AI networking features
  • Multi‑chip simulation:
    Modeling systems with multiple interconnected ASICs
  • Performance optimization:
    Making large‑scale simulations practical
Compensation:

We’re targeting a salary range of $150,000 – $180,000 for this role.Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Upscale AI is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants…

Position Requirements
10+ Years work experience
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