Senior Mixed Signal IP Enablement and Debug Engineer

About The Role

Join Intel's Hard IP Development Group (HIPD) within the Central Engineering Organization, where innovation meets execution. Our team develops industry-leading intellectual property that powers high-performance products across Server, Client, and Networking SoCs, as well as solutions for Intel Foundry customers.

• Provide response for IP questions to customers in a timely manner.
• Provide IP reviews, lab demos, and training to customers as needed.
• Generate industry‑standard IP documentations and collaterals as needed for external customers.
• Partner closely with SoC customers and IP design teams to deliver comprehensive pre‑silicon to post‑silicon IP integration and debug support.
• Develop and execute test plans and content using AI‑driven tools and Python/System Verilog scripting.
• Conduct SoC board design reviews and provide technical recommendations.
• Perform signal integrity and power integrity simulations to optimize design performance.

• Serve as the IP team representative during SoC power‑on activities for test chips and products.
• Provide hands‑on IP enabling support throughout the silicon bring‑up process.
• Lead identification, investigation, and resolution of IP‑related silicon issues.
• Execute timely debugging and disposition of customer issues and sightings.

• Conduct both pre‑silicon and post‑silicon issue reproduction and analysis.
• Drive root cause analysis initiatives with comprehensive failure analysis.
• Collaborate across cross‑functional teams to deliver robust solutions.
• Maintain customer obsession by ensuring rapid resolution of IP‑related challenges.

• Able to work independently with design team and customers to solve issues either remotely or onsite.
• Able to lead on IP debugging as situations arise in addition to hands‑on debug.

• Bachelor's degree and 7+ years of experience or Master's degree and 4+ years of experience in Computer Engineering, Electrical Engineering, or a related field.
• Experience in IP integration, pre‑silicon verification, electrical or functional post‑silicon validation and debug with either serial IOs (PCIe, USB, SATA, Type‑C, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die‑to‑Die).
• 2+ years of experience with lab hardware and software.
• Experience using oscilloscopes, logic analyzers, protocol analyzers, and BERTs (Bit Error Ratio Testers).
• Experience with at least one or more industry‑standard IO specifications like DDR, LPDDR, PCIe, USB, USB Type‑C, Die‑to‑Die, Ethernet, etc. Either PHY or controller experience is good.

• Ph.D. degree in Computer Engineering, Electrical Engineering, or a related field.
• Experience in signal integrity, power delivery, IBIS‑AMI model development and silicon co‑relation.
• Pre‑silicon design or simulation experience in logic, circuits, firmware or MRC and mixed‑signal validation.

• You will play a pivotal role in ensuring Intel's IP portfolio meets the demanding requirements of next‑generation computing platforms. Your work will directly impact product success across multiple market segments while advancing the state‑of‑the‑art in high‑speed IO technologies.
• This position offers the unique opportunity to work at the intersection of cutting‑edge IP development and real‑world customer applications, making you an integral part of Intel's continued innovation leadership.

Experienced Hire

Shift 1 (United States of America)

US, California, Folsom

US, California, Santa Clara

The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

All qualified…