SoC Integration Engineer

About The Role

The Unified Intel Chassis (UIC) team develops scalable chassis architectures and Network-on-Chip technologies that power multiple SoCs inside Intel. We create high-performance, reusable IP components that enable product teams to deliver industry-leading performance while optimizing power and area efficiency.

We are seeking an experienced SoC Integration Engineer to join our world-class team and work on cutting-edge technology that impacts millions of devices worldwide.

• Partner with SoC architecture teams to define and refine system-level chassis and interconnect requirements.
• Design and integrate high-performance NoC/interconnect fabrics meeting power, performance, and area (PPA) targets.
• Drive integration of IP blocks into SoC platforms, ensuring scalability and performance across products.
• Collaborate with fabric IP development teams to enhance or customize reusable components.
• Analyze trade-offs across performance, power, and area to influence architectural decisions.
• Work closely with physical design teams to address floor planning and implementation constraints.
• Support debug, validation, and bring‑up activities for integrated SoC platforms.
• Collaborate across global, cross‑functional teams to deliver complex silicon solutions.

• Systems Thinking:
  Ability to understand and optimize complex SoC ecosystems end-to-end.
• Ownership & Accountability:
  Drives deliverables independently while owning outcomes.
• Collaboration & Influence:
  Builds strong partnerships across architecture, design, and global teams across multiple time zones.
• Technical Leadership:
  Mentors junior engineers and contributes to technical direction.
• Problem Solving:
  Proactively identifies risks and develops scalable solutions.
• Adaptability:
  Thrives in a fast-paced, evolving technology environment.
• Clear Communication:
  Effectively communicates complex technical concepts across audiences.

Minimum qualifications required for initial consideration:

• Bachelor's degree in Electrical Engineering or related field with 6+ years of experience, or a Master's degree in the same field with 4+ years of experience.
• Experience in SOC and/or IP design.

• Experience in microarchitecture and design of IP systems, including 2+ years in fabric design/integration.
• Expertise in Verilog/System Verilog Design, Lint/CDC/RDC, and timing constraints.
• Knowledge of AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL.
• Experience analyzing power, performance and area trade-offs in designs.
• Experience in physical design to understand floorplan limitations.

Intel invests in our people and offers a complete and competitive package of benefits for employees and their families through every stage of life. Find out more about the benefits of working at Intel.

Experienced Hire

Shift 1 (United States of America)

US, California, Santa Clara

US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates…