Senior LPU ASIC Engineer

What You’ll Be Doing

In the role of a Senior LPU ASIC Engineer, you will play a crucial role in our innovative LPU chip design.

• Full-Flow Ownership:
  Responsible for synthesis, floor planning, place & rout, timing constraints, UPF and LEC at the block/partition level and top level.
• Cross-Functional Optimization:
  Partner with IP, Front‑End logic design and Architecture teams to streamline IP integration, drive PPA optimizations, resolving architectural bottlenecks to enable efficient physical implementation.
• Tapeout Execution:
  Lead design closure in collaboration with IP, PnR, Sign‑off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout.
• Methodology Innovation:
  Architect data‑driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.

Qualifications and

Experience:

• B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred) with 5+ years of industry experience delivering full‑flow physical design for large‑scale, high‑performance SoCs at advanced process nodes.
• Full‑Flow Execution:
  Proven track record of driving designs through the complete RTL‑to‑GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification.
• Low‑Power Expertise:
  Deep understanding of low‑power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi‑voltage domain architectures.
• Clock & Timing Mastery:
  Expert‑level proficiency in advanced CTS methodologies, clock tree synthesis, and sign‑off timing analysis (MCMM STA) using complex constraints.
• PPA Optimization:
  Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle.
• Sign‑off & Integrity:
  Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure.
• DFT & Block‑Level Integration:
  Skilled in employing best‑known methods to optimize and handle DFT structures within block‑level physical design implementations.
• EDA Tool Proficiency:
  Expert‑level command of industry‑standard tool suites for end‑to‑end physical design flows.
• Automation & Innovation:
  Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward‑looking ability to integrate AI‑driven optimizations for enhanced design efficiency.
• High‑Speed IP Integration:
  Specialized experience in the physical design of blocks and partitions containing high‑speed Ser Des IPs, such as PCIe, CXL, C2C, and Die‑to‑Die interfaces a plus.

We offer highly competitive salaries and a comprehensive benefits package. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $136,000 USD – $218,500 USD for Level 3, and $168,000 USD – $264,500 USD for Level 4. You will also be eligible for equity and benefits.

Applications for this job will be accepted until June 8, 2026. NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.