Senior SoC Compute​/Memory Subsystem Architect

About The Role

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.

This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.

• Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs
• Architect compute subsystem roles (control plane, data plane assist, offload execution, management services)
• Drive compute architecture decisions balancing performance, power, and area

• Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache)
• Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions)
• Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity

• Architect system memory subsystems including:
• DDR / LPDDR interfaces
• Memory controllers and scheduling policies
• Bandwidth provisioning and scaling strategies
• Work with Performance architect in define memory access models for compute, network, and accelerator subsystems
• Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads

• Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads
• Architect features such as:
• Multi-tenant isolation and security boundaries
• Shared vs isolated memory models
• Ensure efficient interaction between host, IPU/DPU compute, and offload engines

• Architect integration between:
• Compute subsystem
• Network subsystem (packet processing pipelines)
• Storage and accelerator subsystems
• Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead
• Drive system architecture decisions for balanced SoC performance

• Define compute and memory strategies for power efficiency and DVFS scalability
• Architect mechanisms for:
• Memory bandwidth throttling / prioritization
• Per-subsystem scaling
• Optimize performance-per-watt at system level

• Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations
• Define scaling strategies for:
• Core count and frequency
• Memory bandwidth and capacity
• Cache scaling and topology
• Ensure backward compatibility and smooth migration across product lines

• Collaborate with teams across:
• Networking subsystem (NSS)
• SoC fabric/interconnect
• Firmware, OS, and drivers
• Validation and performance modeling and testing
• Drive architecture alignment and resolve cross-domain tradeoff

• Strategic thinker:
  Ability to define long-term architecture vision and align stakeholders
• Technical leadership:
  Influences across teams without direct authority
• Problem solver:
  Approaches complex system challenges with structured thinking
• Collaboration:
  
  Builds strong partnerships across engineering disciplines
• Customer-focused mindset:
  Translates real-world workload needs into solutions
• Adaptability:
  Navigates ambiguity and evolving technical requirements
• Ownership mindset:
  Drives initiatives from concept through execution

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