Senior Mixed Signal IP Enablement and Debug Engineer

About the Role

Join Intel's Hard IP Development Group (HIPD) within the Central Engineering Organization, where innovation meets execution. Our team develops industry‑leading intellectual property that powers high‑performance products across Server, Client, and Networking SoCs, as well as solutions for Intel Foundry customers. HIPD creates a comprehensive portfolio of cutting‑edge Mixed Signal IPs including PLLs, Serial and Parallel IO PHYs (DDR/LPDDR, PCIe, USB, Type‑C, UCIe Die‑to‑Die), and Ethernet PHYs.

As part of our IO Post‑Silicon Validation Debug team, you’ll work with a dynamic group of engineers who serve as the critical bridge between IP design teams and SoC customers throughout the validation and debug process.

• Partner closely with SoC customers and IP design teams to deliver comprehensive pre‑silicon to post‑silicon IP Integration and Debug support.
• Develop and execute test plans and content using AI‑driven tools and Python/System Verilog scripting.
• Conduct SoC board design reviews and provide technical recommendations.
• Perform signal integrity and power integrity simulations to optimize design performance.
• Serve as the IP team representative during SoC power‑on activities for test chips and products.
• Provide hands‑on IP enabling support throughout the silicon bring‑up process.
• Lead identification, investigation, and resolution of IP‑related silicon issues.
• Execute timely debugging and disposition of customer issues and sightings.
• Conduct both pre‑silicon and post‑silicon issue reproduction and analysis.
• Drive root‑cause analysis initiatives with comprehensive failure analysis.
• Collaborate across cross‑functional teams to deliver robust solutions.
• Maintain customer obsession by ensuring rapid resolution of IP‑related challenges.

• Ability to work independently with design team and customers to solve issues either remotely or onsite.
• Ability to lead on IP debug as situation arises in addition to hands‑on debug.

• Bachelor’s degree and 5+ years of experience or Master’s degree and 3+ years of experience in Computer Engineering, Electrical Engineering, or in a related field.
• Experience in IP Integration, pre‑silicon verification, Electrical or Functional Post‑Silicon validation and debug with either serial IOs (PCIe, USB, SATA, Type‑C, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die‑to‑Die).
• 2+ years of experience with lab hardware and software.
• Experience using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs (Bit Error Ratio Testers).
• Experience with at least one or more industry standard IO specifications like DDR, LPDDR, PCIE, USB, USB Type‑C, Die‑to‑Die, Ethernet, etc.
• Either PHY or Controller experience is good.

• Ph.D. degree in Computer Engineering, Electrical Engineering, or a related field.
• Experience in signal integrity, power delivery, IBIS‑AMI model development and silicon co‑relation.
• Pre‑silicon design or simulation experience in logic, circuits, firmware or MRC and mixed‑signal validation.

You’ll play a pivotal role in ensuring Intel’s IP portfolio meets the demanding requirements of next‑generation computing platforms. Your work will directly impact product success across multiple market segments while advancing the state‑of‑the‑art in high‑speed IO technologies. This position offers the unique opportunity to work at the intersection of cutting‑edge IP development and real‑world customer applications, making you an integral part of Intel’s continued innovation leadership.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)
Work Model:
Hybrid – split time between on‑site at your assigned Intel site and off‑site.

Primary

Location:

US, California, Folsom
Additional Locations: US, California, Santa Clara

We offer a total compensation package that ranks among the best in the industry. It includes competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation. Annual Salary Range for jobs in the US: $–$ USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations; individual pay is determined by location and additional factors.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.