Director, SoC Design Engineering

Role Overview

We are seeking a highly experienced Director, SoC Design Engineering, to lead the functional verification efforts for cutting‑edge system-on‑chip (SoC) designs. In this strategic role, you will define and implement scalable and reusable verification methodologies that ensure first‑pass silicon success and drive innovation that strengthens Intel's leadership in the semiconductor industry.

• Architect and define end‑to‑end SoC verification strategies, including simulation, emulation, and formal verification approaches, to validate complex SoC designs.
• Develop and execute block, subsystem, and SoC‑level verification plans, including test benches and coverage models, to ensure compliance with microarchitecture specifications.
• Lead verification closure for critical interfaces such as AXI, ACE, CHI, and interconnect fabrics.
• Collaborate with SoC architects, RTL designers, and firmware teams to define verification hooks, assertions, and coverage metrics.
• Oversee the integration of multiple IPs such as PCIe Gen6/7, DDR5/6, and Ethernet into the SoC environment, driving verification success.
• Define and promote reusable UVM‑based verification methodologies and automation flows to improve team productivity.
• Lead emulation and performance modeling efforts, including co‑verification of digital designs with firmware and architectural simulations using advanced platforms like Palladium and Veloce.
• Debug and root‑cause complex issues in pre‑silicon environments, implementing corrective measures to ensure design functionality and performance.
• Provide expert guidance and mentorship to technical leads and design verification engineers, fostering a culture of continuous learning and improvement.
• Collaborate with post‑silicon validation teams to incorporate learnings into future verification methodologies and infrastructure.

• Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or related field, with 12+ years of relevant experience.
• 5+ years of people management experience.
• Expertise in System Verilog and UVM/OVM verification methodologies.
• Comprehensive knowledge of SoC microarchitecture, including coherency protocols, cache subsystems, and interconnect fabrics.
• Proven experience with high‑speed protocols such as PCIe, DDR, AXI, CHI, or NoC.
• Hands‑on experience with emulation and prototyping platforms such as Palladium, Veloce, FPGA‑based systems, and formal verification tools.
• Demonstrated ability to develop and maintain verification environments, including scoreboards, monitors, and VIP integration.
• Masters degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of work experience, or PhD with 6+ years of experience (preferred).
• Familiarity with power intent verification (UPF) and security verification techniques (preferred).
• Experience with AI/ML accelerators, custom interconnect fabrics, or SmartNIC technologies (preferred).
• Strong scripting skills in Python, Perl, or TCL to automate verification flows and regressions (preferred).
• Proven ability to drive pre‑silicon to post‑silicon correlation for continuous improvement (preferred).
• Exceptional analytical, debugging, and technical leadership abilities, with a passion for driving innovation and excellence (preferred).

This role is a Position of Trust. If accepted, you must consent to and pass an extended background investigation, including education verification and criminal checks.

Annual Salary Range:

- USD

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.