Senior EDA Tools Software Engineer

Job Overview

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud‑to‑edge technology is at the heart of countless innovations. With a career at Intel, you’ll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life.

Join us and help make the future more wonderful for everyone.

• Architect, design, and implement a new chassis automation tool to meet requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibility.
• Analyze chassis and interconnect architecture specifications and high‑level SoC requirements, building tooling to translate these into generated outputs such as RTL, RDL, verification collateral, timing, and integration artifacts.
• Develop automation flows that convert architectural intent into concrete implementations, including topology generation, parameter derivation, register definitions, and associated collateral.
• Integrate with frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (RTL, Verilog, SDC, RDL), ensuring correctness and consistency.
• Enable PPA optimization loops by building automation and analysis capabilities that evaluate design trade‑offs and guide configuration decisions.
• Work closely with architecture, RTL design, verification, and SoC integration teams to ensure the tool captures requirements and produces outputs that meet downstream expectations.
• Participate in and contribute to technical reviews with cross‑functional stakeholders, incorporating feedback to improve tool capabilities, usability, and quality.
• Lead end‑to‑end execution from initial concepts and specifications through development, deployment, and ongoing maintenance of the automation framework.
• Deliver the tool and associated outputs to multiple internal customers, balancing competing requirements, schedules, and priorities while maintaining high quality.
• Collaborate across organizational boundaries to unblock execution and ensure overall program success.
• Mentor and guide engineers, helping establish best practices in software design, testing, and maintainability, elevating overall team effectiveness.

• Minimum Qualifications:
• Bachelor’s degree in Electrical Engineering, Computer Science, or a related field, with 9+ years of experience in CAD/EDA tooling, design automation, or semiconductor development; OR Master’s degree with 8+ years of experience.
• 5+ years of experience building scalable, maintainable software systems and frameworks.
• 4+ years of experience in Python or similar language designing and validating structured schemas using JSON or YAML.
• 2+ years of experience with digital SoC design concepts, RTL hierarchy, synthesis flows, and parameterized IP design.
• 2+ years of experience with System Verilog to understand and validate generated design outputs.
• 2+ years of experience with templating systems or code generation frameworks used for structured RTL or collateral generation.
• 1+ year of experience with version control (Git), code reviews, unit/integration testing, and CI/CD practices.
• Preferred Qualifications:
• Experience building and developing EDA tooling.
• Experience with NoC architectures or high‑performance interconnect protocols such as AXI, CHI, PCIe, UCIe, or similar.
• Familiarity with IP packaging, configuration, and integration methodologies, including IP‑XACT standards.
• Exposure to industry EDA tools and design flows.
• Knowledge of graph‑based algorithms (e.g., NetworkX) and data structures relevant to topology generation, connectivity modeling, or routing problems.
• Prior experience working in a semiconductor product development environment, such as CAD, RTL design, or verification.
• Experience in GUI development.

Annual Salary Range: $ – $ USD.

Intel offers a total rewards package that includes competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation. Further details are available on Intel Careers.

Type:
Experienced Hire

Shift: Shift 1 (United States of America)
Primary

Location:

US, California, Santa Clara
Business Group:
Central Engineering Group (CEG) – Product Enablement, Custom ASIC, Foundry Enablement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.