SoC Integration Engineer

About the Role

The Unified Intel Chassis (UIC) team develops scalable chassis architectures and Network-on-Chip technologies that power multiple SoCs inside Intel. We create high-performance, reusable IP components that enable product teams to deliver industry-leading performance while optimizing power and area efficiency. We are seeking an experienced SoC Integration Engineer to join our world‑class team to work on cutting‑edge technology that impacts millions of devices globally.

In this role, you will work on integration and development of high-performance Network-on-Chip (NoC) platform solutions, working closely with SoC architecture, IP, and physical design teams to deliver optimized silicon platforms.

• Partner with SoC architecture teams to define and refine system‑level chassis and interconnect requirements
• Design and integrate high-performance NoC / interconnect fabrics meeting power, performance, and area (PPA) targets
• Drive integration of IP blocks into SoC platforms, ensuring scalability and performance across products
• Collaborate with fabric IP development teams to enhance or customize reusable components
• Analyze trade‑offs across performance, power, and area to influence architectural decisions
• Work closely with physical design teams to address floor planning and implementation constraints
• Support debug, validation, and bring‑up activities for integrated SoC platforms
• Collaborate across global, cross‑functional teams to deliver complex silicon solutions

• Systems Thinking: Ability to understand and optimize complex SoC ecosystems end-to-end
• Ownership & Accountability: Drives deliverables independently while owning outcomes
• Collaboration & Influence: Builds strong partnerships across architecture, design, and global teams across multiple time zones
• Technical Leadership: Mentors junior engineers and contributes to technical direction
• Problem Solving: Proactively identifies risks and develops scalable solutions
• Adaptability: Thrives in a fast‑paced, evolving technology environment
• Clear Communication: Effectively communicates complex technical concepts across audiences

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Bachelor's degree in Electrical Engineering or related field with 6+ years of experience.
• Master's degree in the same field with 4+ years of experience.
• Experience in SOC and/or IP design.

• Experience in microarchitecture and design of IP systems, including 2+ years' experience in fabric design/integration.
• Expertise in Verilog/System Verilog design, lint/CDC/RDC and timing constraints.
• AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL knowledge.
• Experience in analyzing power, performance and area trade‑offs in designs.
• Physical design knowledge to understand floorplan limitations.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Job Type: Experienced Hire

│ Shift: Shift 1 (United States of America) │ Primary

Location:

US, California, Santa Clara │ Additional Locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin │ Business Group:
The Central Engineering Group (CEG) │ Salary Range: $– USD │ Work Model:
Eligible for hybrid work with split on‑site and off‑site.