Senior Logic Design Engineer

We are now looking for a Senior Logic Design Engineer! As part of the DGX FPGA Logic Team, you will take charge of a section of FPGA/CPLD development, focusing on micro-architectural definition, RTL coding, logic debug, synthesis, and timing closure. Supporting verification, implementation, system bring-up, and system-level validation/debug are also part of your duties. This position allows you to contribute meaningfully to a vibrant, technology-focused company that drives Data Center products around artificial intelligence growth.

Our outstanding team spans the globe, aiming to extend the boundaries of what is achievable today and invent the platform for future computing.

As a member of our DGX FPGA design team, you will own and be responsible for architecting, designing, and supporting various FPGA/CPLDs. Tasks include:

• Collaborating with the system architecture team to develop FPGA/CPLD design requirements and implement design to meet all specifications and targets.

• Writing readable high‑quality RTL, synthesis, timing closure, design documentation, schematic review, bring‑up, and supporting system‑level validation/debug in the lab.

• Collaborating with our design verification and formal verification team to confirm the accuracy of your design.

• Working together with the validation team to carry out in‑system tests and measurements in the lab.

• Assisting with overall FPGA design activities.

• System bring‑up locally as well as at other global sites, with up to 20% travel expected.

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent experience.

• 5+ years of experience in FPGA/CPLD and/or ASIC semiconductor designs.

• Verilog/System Verilog expertise required, with a deep understanding of ASIC/FPGA/CPLD development flow including RTL development, verification, logic synthesis, prototyping, DFT, timing analysis, and lab bring‑up/debug.

• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, distributed team. Your proven experience mentoring junior engineers and interns is a significant advantage.

• A solid foundation in FPGA/CPLD development and familiarity with FPGA EDA tools from Xilinx, Altera, or Lattice like Vivado, Quartus, or Diamond is highly valued.

• Familiarity with industry‑standard protocols such as I2C, SPI, JTAG, PCIE, USB, Ethernet, Encryption as well as languages such as embedded C, Python, Perl is a plus.

• Willingness and ability to travel up to 20% of the time.

• A track record of collaborating across Systems, Firmware, Software, AE, and Operations teams.

• Direct involvement in system bring‑ups.

• Platform and system design:
  Strong understanding or practical experiences with system design methodologies including board design, SI and familiarity with schematics and layout tools.

• Cross‑functional collaboration:
  Excel in cross‑functional collaboration between firmware and hardware teams, which is crucial during design development, bring up and working through customer issues.

• Automation and AI:
  Ability to adopt AI to automate tasks efficiently, which includes but not limited to RTL generation, FPGA/CPLD build process and system level validation.

Join us and be part of a team that is pushing the boundaries of technology and making a lasting impact on the world!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.