Physical Design Engineer - Levels at Qualcomm Santa Clara, CA

Physical Design Engineer – Multiple Levels

Company: Qualcomm Technologies, Inc.

Job Area: Engineering Group, Engineering Group > ASICS Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what’s possible to enable next‑generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state‑of‑the‑art tools and technologies.

You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high‑speed, low‑power designs such as GPU, Camera and other MM, DDR, Modem, Audio. Tasks also involve the development and enablement of low‑power implementation methods, customized P&R to achieve area reduction, performance, and power goals.

Additional responsibilities in this role involve good understanding of functional and test (DFT) mode constraints for place and route, floor planning, power planning, IR drop analysis, cell placement, multi‑mode & multi‑corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, crosstalk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification.

The individual should have deep knowledge of scripting and software languages including Python, PERL/TCL, Linux/Unix shell and

C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.

• 2–10+ years industry experience
• Physical Design
• Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
• Timing closure experience in Synopsys PTSI
• Formal verification experience
• Power domain analysis experience
• Physical verification experience

• Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.

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Qualcomm also offers a competitive annual discretionary bonus program and opportunity for annual RSU grants. Benefits include a highly competitive package designed to support success at work, home, and play.