Senior Systems Prototyping and Emulation Engineer

Job Requisition

Job Category Engineering

Time Type Full time

Are you passionate about DGX systems connecting multiple ASIC chips together, FPGA prototyping, and hardware emulation? Are you interested in pushing the boundaries of innovation to make FPGA prototypes and emulation platforms faster, more scalable, and more efficient? Can you work in a fast-paced environment that requires coordination between many teams across geographies and solving sophisticated problems daily? If so, we are looking for hardworking systems engineers who will craft FPGA prototypes and emulation environments for our next generation GPUs, SOCs, NICs, and Switches on industry-standard FPGA prototyping and emulation platforms.

We are now looking for a Senior Systems Prototyping and Emulation Engineer to join our Emulation team onsite in Santa Clara, CA.

• Build FPGA prototypes and hardware emulation environments by making RTL FPGA/emulation-friendly, partitioning the design, and taking it through synthesis, place-and-route, and emulator compilation flows.
• Improve performance of FPGA prototypes and emulation platforms, analyze timing/performance bottlenecks, and generate bitstreams/images.
• Bring up designs on FPGA prototyping and hardware emulation platforms and drive complex debug and problem-solving activities.
• Release prototypes and emulation environments to internal customers and support them through debug, validation, and software enablement.
• Understand the design and implementation, define configurations, develop/modify bring-up and testing infrastructure, and verify correctness of the design.
• Understand complex system topologies with multiple ASICs to realize DGX systems on prototyping platforms and emulators.
• Work closely with architects, designers, verification engineers, validation teams, and software teams to accomplish project goals.
• Enable pre-silicon software development, validation, and performance analysis using FPGA prototypes and hardware emulation environments.
• Develop and optimize emulation-friendly validation infrastructures, including high-performance software interfaces and scalable debug methodologies.

• BS (or equivalent experience) in Electrical Engineering, Computer Engineering, or related fields with 8+ years of experience, or MS with 6+ years of proven experience in FPGA prototyping and/or hardware emulation.
• Strong understanding of FPGA prototyping and hardware emulation architectures, devices, flows, and tools.
• Hands-on experience with Synopsys Proto Compiler or Synplify Premier, Xilinx Vivado, and familiarity with emulation platforms such as Synopsys ZeBu or Siemens Veloce.
• Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB).
• Knowledge of Verilog, System Verilog, and digital design concepts.
• Understanding of industry-standard protocols such as PCIe, CXL, NVLINK, USB, CHI, and CPU-GPU coherency.
• Hands-on experience with lab FPGA debug methodologies, tools (Identify or Chip Scope), and lab debug equipment (oscilloscopes, logic analyzers).
• Strong expertise in developing and optimizing emulation-friendly C/C++ test benches and transactors that can operate efficiently at emulation speeds is a critical skill for this role and experience minimizing host-emulator communication bottlenecks, improving transaction throughput, and architecting scalable software-driven validation environments for high-performance SoCs and multi-ASIC systems.
• Ability to develop efficient DPI/PLI/SystemC-based interfaces and software infrastructures that enable high-speed validation, debug, and bring-up on hardware emulation platforms.

• Scripting knowledge (Perl/shell/Tcl/Python) is desired.
• Good documentation, communication, and interpersonal skills.
• Experience with memory bring-up of LPDDR5/6, DDR5/6, CXL/PCIe, and/or high-speed interfaces such as USB4/3 is desirable.
• Prior experience with hardware emulation or prototyping platforms (Synopsys HAPS, ZeBu, Siemens Veloce) of a high-performance processor or SOC is highly desirable.
• Understanding of performance-sensitive validation methodologies for large-scale emulation environments, including…