Sr ASIC Design Verification Engineer

Our Mission

At Palo Alto Networks®, we're united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place.

In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values:
Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real-world problems and ideating beside the best and the brightest, we invite you to join us! We believe collaboration thrives in person. That's why most of our teams work from the office full time, with flexibility when it's needed.

This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes.

Your Career As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug. You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation.

We expect office-based employees to be in the office four days per week, with one day working from where they choose. We believe being together facilitates casual conversations and those magic moments where we can work on issues and ideas informally. These moments build capability and deepen trusted relationships and allow our people to feel safe in taking risks and being disruptive.

Like so many companies, we are working through the details and things could change... but in general if a role is deemed office-based we want our teams to be together four days per week.

• Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification.
• Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies.
• Develop flows, methodologies, and infrastructure for emulation.
• Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers.
• Define new tools and methodologies to continuously improve quality and velocity.
• Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification.

• BS in EE, CE, or CS required or equivalent military experience required – MSEE preferred.
• Minimum 3 years experience in ASIC design verification.
• Demonstrated success in taking multiple ASIC products from concept to mass production.
• Expertise in System Verilog and UVM.
• Technical strength in the following areas:
  Defining test plans, including comprehensive adversarial testing, developing rich functional coverage models, creating powerful and scalable test benches, implementing sophisticated self-checking infrastructure with reference models and scoreboards, developing reusable constrained-random tests, debugging failures, closing coverage.
• Experience in the following areas preferred:
  Networking and cyber security, formal property verification, silicon validation – bringup, test, debug, and regression, creating models in Python and C/C++, writing driver code in
  
  C.
• Skill in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing.
• Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status.
• Stro…