CPU Server Physical Design Timing Engineer

Company

Qualcomm Technologies, Inc.

Engineering Group > CPU Engineering

NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.

In this role you will define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. One of your primary responsibilities will be coding scripts used with STA native tools and enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm.

You will collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU. You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3.

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
• Find root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.
• Work on automation scripts within STA/PD tools for methodology development.
• Good technical writing and communication skills, should be willing to work in cross-collaborative environment.
• Strong experience in design automation using TCL/Perl/Python.
• Familiar with digital flow design implementation RTL to GDS: ICC, Innovus, PT/Tempus.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of related work experience.
• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of related work experience.

• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, latch transparency handling, 0-cycle, multi-cycle path handling.
• Hands‑on experience with STA tools – Prime-time, Tempus.
• Experience driving timing convergence at Chip‑level and Hard‑Macro level.
• In‑depth knowledge of cross-talk noise, signal integrity, layout parasitic extraction, feed‑through handling.
• Knowledge of ASIC back‑end design flows and methods and tools (ICC2, Innovus).
• Expert in scripting languages – TCL, Perl, Python.
• Basic knowledge of device physics.

Qualcomm is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification. Qualcomm is committed to providing reasonable accommodations for individuals with disabilities during the application and hiring process. If you require accommodations, please contact disabilit

$ – $. In addition to base salary, this role may be eligible for a competitive annual discretionary bonus program and opportunity for annual RSU grants. Qualcomm offers a highly competitive benefits package to support your success at work, at home, and at play.

For more information about this role, please contact Qualcomm Careers.