Power & Clocking Engineer — DVFS/PMU RTL Design; Equity
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-06-18
Listing for:
SiFive
Full Time
position Listed on 2026-06-18
Job specializations:
-
Engineering
Systems Engineer, Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
SiFive in Santa Clara, CA is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design industry-leading CPU and interconnect IP. This role involves collaborating with various teams to architect solutions for power management and clocking, alongside responsibility for thorough verification processes. Candidates should possess extensive experience in CPU and SoC design, familiarity with Verilog/System Verilog, and a BS/MS in a relevant field.
Competitive salary range is from $158,760 to $194,040, with comprehensive benefits.
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