Standard Cell Library Engineer

Job Overview

In this position you will participate in the development and validation of tools, flows, and collaterals related to standard cell library reliability – electromigration, thermal effects, and voltage drop.

• Workflow optimization
• Vendor engagement for tool requirements and development
• Foundry engagement for tool requirements
• Customer facing documentation
• Developer facing documentation
• Collateral generation
• Collateral validation across multiple usage scenarios

• Bachelor's degree in Electrical Engineering or a related field with 3+ years of professional work experience
• Master's degree in Electrical Engineering or a related field with 2+ years of professional work experience
• Understanding of electromigration and thermal effects on transistors and interconnect
• Strong written and verbal communication skills with the ability to tailor communication based on the audience

• Unix proficiency
• Basic software skills using command line languages (csh, bash, perl, python)
• Innovative thinker ready to make an impact in the evolving semiconductor landscape

Annual Salary Range: $ –  USD. Pay is determined by work location and additional factors, including job‑related skills, experience, and education.

Hybrid model allows employees to split time between on‑site at the assigned Intel site and off‑site.

Primary

Location:

US, California, Santa Clara
Additional Locations: US, California, Folsom
Shift: Shift 1 (United States of America)

Competitive pay, stock bonuses, and benefit programs that include health, retirement, and vacation.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.