CPU Power-Management Design Engineer

About Si Five

SiFive is a leading company transforming computing with the open RISC‑V architecture, providing high‑performance, data‑intensive solutions across AI, machine learning, automotive, data center, mobile, and consumer markets.

SiFive seeks a Power‑Management/Reset/Clock Micro‑Architect and RTL Design Engineer to design industry‑leading CPU and interconnect IP, enabling rapid adoption of RISC‑V across a broad range of verticals.

• Work with the architecture team to understand and define power‑management requirements.
• Architect, design and implement core clocking, reset and power‑management solutions.
• Develop micro‑architecture specifications.
• Document knowledge and collaborate openly with team members.
• Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
• Collaborate with the physical implementation team to optimize physical design for frequency, area and power goals.
• Partner with the software team to enable and optimize power‑management features.

• 3+ years recent industry experience in CPU and SoC clocking, reset, and power‑management design.
• Experience in high‑performance, energy‑efficient CPU and SoC designs.
• Expertise in CPU and SoC clocking, reset, and power‑management, including:
• Reset control and design strategies: clock distribution, dynamic clocking, clock gating, and clock‑boundary crossing.
• Power state definition and management;
  Power Management Unit (PMU) design.
• Dynamic and static power‑reduction techniques, including retention and power‑up/down sequencing.
• Dynamic voltage and frequency scaling (DVFS) and DI/dT mitigation strategies.
• Understanding of DFT, MBIST, debug and error handling in CPU designs.
• Power‑aware simulation.
• Proficient in RTL design in Verilog, System Verilog, or VHDL.
• Strong grasp of RTL quality checks (Lint, CDC, RDC, etc.).
• Hands‑on experience with Spyglass is a plus.
• Attention to detail and focus on high‑quality design.
• Strong teamwork and communication skills.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Background in successful CPU or SoC development from architecture through tapeout.
• BS/MS degree in EE, CE, CS or related discipline, or equivalent experience.

• Experience with AMBA Interconnect Protocols (AXI, AHB, APB).
• Experience with AMBA Low Power Protocol Interface (P‑channel, Q‑channel).
• Experience with Scala/Chisel, Bluespec, or similar DSL for configurable hardware.
• Knowledge of RISC‑V architecture.
• Experience with Git/Git Hub, Jira, Confluence.

• Base pay range: $ – $ (varies by location).
• Eligible for variable/incentive compensation and/or equity.
• Comprehensive benefits: medical, vision, dental, 401(k) plan, employee stock option program.
• Flexible paid time off and other benefits.

SiFive is proud to be an equal employment opportunity workplace.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

All applicants will be required to complete a Form I‑9 and, if applicable, the E‑Verify process.