Senior RTL Engineer

About Velaura

Velaura is building the next generation of compute platforms for Physical AI.

As AI moves beyond the datacenter into robots, autonomous mobile systems, drones, and other embodied systems, traditional compute architectures are increasingly constrained by power, memory bandwidth, latency, real-time requirements, and functional safety considerations.

Our mission is to develop the foundational compute technologies that enable intelligent systems to operate efficiently in the physical world.

We are assembling a team of exceptional architects and engineers to rethink how AI, sensing, memory, and control interact within a modern computing platform.

Role Overview

We are looking for a Senior RTL Engineer to help build Velaura's next-generation Physical AI SoC.

In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, and physical design teams to transform innovative architectural concepts into production silicon. You will own significant portions of the design, drive microarchitectural decisions, and help deliver high-performance, power-efficient hardware that enables the next generation of intelligent physical systems.

Responsibilities

* Own the design, implementation, and optimization of RTL for key portions of the Velaura SoC.

* Collaborate with architects to develop robust and efficient microarchitectures, and drive microarchitectural decisions within your areas of ownership.

* Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.

* Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.

* Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.

* Optimize designs for performance, power, area, scalability, and reliability.

* Partner closely with verification and physical design teams throughout the development cycle, and mentor junior engineers on design methodology and microarchitecture.

* Analyze performance bottlenecks and propose architectural and implementation improvements.

* Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.

* Participate in and lead design reviews, contributing to a culture of technical excellence.

Desired Experience

* 8+ years (or equivalent depth) designing RTL for complex digital systems, with demonstrated ownership of significant blocks or subsystems through tapeout.

* Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.

* Expert-level Verilog/System Verilog and modern RTL design methodologies (lint, CDC, synthesis-aware coding, low-power intent).

* Strong grasp of performance, power, and area tradeoffs, and experience making data-driven microarchitecture decisions.

* Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.

* Experience with hardware/software co-design and system-level performance optimization.

* Strong debugging and problem-solving skills.

* Ability to work effectively in - and technically lead within - a collaborative, multidisciplinary engineering environment.

Preferred Qualifications

* Deep expertise in memory subsystem design: caches, coherency, memory controllers (e.g., LPDDR/DDR/HBM), on-chip SRAM organization, address translation, and memory protection.

* Hands-on experience designing or significantly extending DMA engines, data-movement accelerators, or similar high-bandwidth data-path logic - including descriptor-based DMA, multi-channel arbitration, QoS, and outstanding-transaction management.

* Working knowledge of standard interconnect and coherency protocols (e.g., AXI, CHI, ACE) and their performance implications.

* Experience with SMMU/IOMMU design or integration, virtualization, and DMA isolation for safety or security.

* Familiarity with RAS features in memory and data paths, such as ECC, poisoning, and error reporting.

* Experience with NoC fabrics, virtual…