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Senior ASIC Verification Engineer: Pre-Silicon Impact

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Palo Alto Networks, Inc.
Full Time position
Listed on 2026-06-19
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 106400 - 172150 USD Yearly USD 106400.00 172150.00 YEAR
Job Description & How to Apply Below

Palo Alto Networks, Inc. is seeking a Design Verification Engineer for the ASIC team to ensure ASICs meet industry-leading requirements for performance and reliability.

This role involves defining verification methodologies and collaborating with engineers across teams to create comprehensive verification plans. Candidates should have a BS in Electrical Engineering, Computer Engineering, or Computer Science, with at least 3 years of experience in ASIC design verification.

The position offers a competitive salary range from $106,400 to $172,150 per year, depending on qualifications and experience.

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Position Requirements
10+ Years work experience
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