Senior ASIC Timing Engineer, DFT

DFT Timing Engineer – Overview

We are seeking a motivated DFT‑Timing Engineer to join our dynamic team. The role focuses on driving timing analysis and closure for DFT logic across all NVIDIA chips (GPUs/CPUs/DPUs/LPUs/SoCs) at every hierarchical level.

• Drive timing analysis and closure for DFT logic on all NVIDIA chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full‑chip).
• Collaborate with PD, DFX, Clocks, and other teams to develop timing closure strategy, timing constraints for custom DFT designs, and drive timing and power convergence.
• Implement ECOs and continuously improve workflows and designs by introducing automation, resilience, and standardization.

• BS in Electrical or Computer Engineering with 5+ years of experience, or MS with 2+ years of experience (or equivalent).
• Hands‑on experience in Static Timing Analysis (STA) and driving timing convergence at full‑chip/sub‑chip level in advanced technology nodes.
• Expertise in analyzing and fixing timing paths through ECOs and in developing timing constraints.
• In‑depth knowledge of industry‑standard timing convergence tools.
• Desirable:
  Understanding of DFT logic and experience with DFT timing closure for various modes (scan, iJTAG, etc.), background in domain‑specific STA and timing convergence (Serdes, Processor, IO, SMVA, etc.), and experience in methodology and/or workflow development.

• Base salary range: 136,000
  
  USD – 218,500
  
  USD for Level3, and 168,000
  
  USD – 264,500
  
  USD for Level
  4.
• Eligibility for equity and additional benefits.

NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law. Applications for this job will be accepted at least until June
15,2026.