US_West | Manufacturing & Process Engineer_L

Position: US_West | Manufacturing & Process Engineer_L3
Description:

Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype , VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.

Submit candidates under their legal name and use only Capgemini template
Candidate's photo  MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.

In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype )
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to

Vendors:
If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.

Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email:

Role:
Analog Layout Engineer

Location:

Santa Clara, CA

JOB DESCRIPTION
MUST HAVE:

Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, 16nm, following best practices from the industry.

Qualifications

• Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.

• Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.

• Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.

• Experience with floor planning, block level routing and top-level chip assembly.

• Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.

• Demonstrated experience with analog layout for silicon chips in mass production.

• Experience with FinFET process nodes preferred

• Experience working with distributed design teams a plus.

• Knowledge of skill code and layout automation a plus.

• Self-starter with the ability to define and adhere to a schedule.

• Must possess strong written and verbal communication skills.

• 10+ years' experience in high performance analog layout in advanced CMOS process.

• Experience in IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm

• LVS, DRC, ERC

• Knowledge of high-performance analog layout techniques
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details

• Global Grade : C
• Named Job Posting? (if Yes - needs to be approved by SCSC) :
  No
• Remote work possibility :
  No
• Global Role Family : 61404 (P) Manufacturing & Process Engineering
• Global Technical Skills Family : 18611 (F) Product Engineering
• Local Role Name :
  Analog Layout Engineer
• Local Skills :
  Julie Skidmore
• Languages
  
  Required:
  
  :
  English