Physical Design Flow Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.

Tenstorrent is looking for seasoned Physical Design Flow Engineers to develop implementation flows and methodologies for high performance, low power designs on advanced technology nodes, with focus on improving Power, Performance, and Area (PPA) in taped-out designs for its next gen products.

• BS/MS in Electrical or Computer Engineering, or equivalent experience, with 5+ years in Physical Design and CAD methodology development.
• Strong track record of building implementation flows for high performance, low power designs on advanced nodes and delivering measurable PPA improvements in silicon.
• Hands-on with industry-standard EDA tools such as Fusion Compiler across synthesis, place-and-route, static timing analysis, and sign-off closure.
• Proficient in hierarchical design flows, physical design verification, and scripting in Tcl, Python, or Perl to improve automation, robustness, and efficiency.

• Lead and contribute to cross-functional efforts that solve complex physical design challenges across multiple IPs, projects, and technology nodes.
• Develop and maintain RTL-to-GDS methodologies covering floor planning, synthesis, place-and-route, static timing analysis, sign-off, and chip assembly.
• Optimize EDA tools, flows, and custom CAD solutions to improve PPA, runtime, automation, and overall engineering productivity.
• Partner closely with physical verification, RC extraction, timing, and DFT teams while driving innovative ML-based approaches to design optimization.
• Apply advanced AI and high-performance silicon practices to shape physical design methodology choices.
• Implement best practices for integrating implementation, sign-off, PV/EMIR, RC extraction, STA, and DFT into a unified, high-yield methodology.
• Apply data-driven and ML-based techniques to flow optimization and influence EDA vendor roadmaps based on real production needs.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. export-controlled technology. Due to U.S. export laws, including those codified in the Export Administration Regulations (EAR), the company is required to ensure compliance with these laws when transferring technology to nationals of certain countries. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship or permanent residency status or ability to obtain prior license approval.