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EDA Design Flow Development Engineer

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Intel Corporation
Full Time position
Listed on 2026-06-19
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Hardware Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 200000 - 250000 USD Yearly USD 200000.00 250000.00 YEAR
Job Description & How to Apply Below

Role Overview

Join Intel in shaping the future of technology. As an EDA Tools Hardware Engineer, you will play a pivotal role in enabling groundbreaking innovations that power Intel's leadership in semiconductor design and manufacturing. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros across advanced semiconductor technologies.

This role focuses on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification. The engineer will work closely with circuit design, physical design, package, reliability, and signoff teams to enable scalable and accurate EM/IR analysis methodologies for advanced-node designs.

The ideal candidate has strong expertise in transistor-level power integrity analysis, SPICE-based verification, parasitic-aware reliability modeling, and automation development using industry-standard EM/IR signoff tools.

Qualifications
  • Minimum Qualifications
    • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field, and 6+ years of experience; 4+ years of experience with a Master's degree; or 2+ years of experience with a PhD.
    • EM/IR reliability concepts (Electromigration, and Power Drop).
    • Experience with Redhawk/Totem tools.
  • Preferred Qualifications
    • Experience in the following:
      • CMOS circuit operation
      • Power delivery networks
      • SPICE simulation
      • Parasitic extraction fundamentals
      • Advanced-node design challenges
      • Transistor-level power integrity analysis flows
      • Scripting and automation skills in Linux environments
Job Details

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)
Primary

Location:

US, California, Santa Clara
Additional Locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range

$- USD

Work Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Equal Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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