Senior SoC Compute​/Memory Subsystem Architect

Overview

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.

• Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs.
• Architect compute subsystem roles (control plane, data plane assist, offload execution, management services).
• Drive compute architecture decisions balancing performance, power, and area.
• Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache).
• Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions).
• Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity.
• Architect system memory subsystems including DDR/LPDDR interfaces, memory controllers, scheduling policies, and bandwidth provisioning strategies.
• Work with Performance architects to define memory access models for compute, network, and accelerator subsystems.
• Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads.
• Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads.
• Architect features such as multi-tenant isolation, security boundaries, shared vs isolated memory models.
• Ensure efficient interaction between host, IPU/DPU compute, and offload engines.
• Architect integration between compute, network, storage, and accelerator subsystems, optimizing data movement to minimize copies, latency, and bandwidth overhead.
• Define compute and memory strategies for power efficiency and DVFS scalability.
• Architect mechanisms for memory bandwidth throttling/prioritization and per-subsystem scaling.
• Optimize performance-per-watt at system level.
• Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations, ensuring backward compatibility and smooth migration.
• Collaborate with cross-functional teams (Networking, SoC fabric/interconnect, Firmware, OS, drivers, validation, performance modeling) to drive architecture alignment and resolve tradeoffs.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a STEM-related field.
• 7+ years of experience in SoC/CPU/memory subsystem architecture, CPU architecture and cache hierarchies, memory subsystems (DDR/HBM), coherent/non-coherent interconnect architectures, and system-level performance and PPA tradeoff analysis.
• Experience defining architecture from concept to silicon.

• Postgraduate degree in Electrical Engineering, Computer Engineering, or a STEM-related field.
• Experience with ARM and x86 compute and memory subsystems, including NUMA systems and large scale platform architectures.
• Experience with IPU/SmartNIC or accelerator-centric SoCs, particularly in cloud and hyperscale environments.
• Familiarity with PCIe, CXL, and memory semantics for high-performance IO.
• Track record of multi-generation architectural ownership and mentoring other architects.

• Strategic thinker:
  Ability to define long-term architecture vision and align stakeholders.
• Technical leadership:
  Influences across teams without direct authority.
• Problem solver:
  Approaches complex system challenges with structured thinking.
• Collaboration:
  
  Builds strong partnerships across engineering disciplines.
• Customer-focused mindset:
  Translates real-world workload needs into solutions.
• Adaptability:
  Navigates ambiguity and evolving technical requirements.
• Ownership mindset:
  Drives initiatives from concept through execution.

Job Type: Experienced Hire |

Shift: Shift 1 (United States) | Primary

Location:

Santa Clara, CA | Additional Locations:
Phoenix, AZ;
Folsom, CA;
San Jose, CA;
Fort Collins, CO;
Austin, TX

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a competitive compensation package that includes base pay, stock bonuses, health benefits, retirement plans, and paid vacation. The salary range for U.S. locations is $ – $.