EDA Tools Hardware Engineer

Overview

Join Intel's mission to engineer world‑changing technology as an EDA Tools Hardware Engineer. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor‑level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler‑generated macros across advanced semiconductor technologies.

This role focuses on characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will work closely with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon‑accurate timing, power, and noise modeling flows.

The ideal candidate has strong expertise in SPICE‑based characterization, Liberty model generation, custom macro timing behavior, and large‑scale automation using industry‑standard tools such as Synopsys Nano Time and Cadence Liberate.

• Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance.
• Collaborate with EDA vendors to define, evaluate, and test next‑generation design tools and flows.
• Create and verify unique hardware designs, integrating components into hierarchical systems to support end‑to‑end EDA tool testing for advanced technology nodes.
• Define and enable methodologies for hardware development related to EDA tools and technology node advancements.
• Support and enhance platforms, databases, scripts, and tools used for design automation.
• Provide digital design, verification, full‑chip integration, physical layout, power, performance, clocking, and timing for future TFM development.

• Minimum Qualifications:
  
  Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field and 6+ years of relevant experience; OR Master’s degree and 4+ years of experience; OR PhD and 2+ years of experience.
• Experience with timing characterization methodologies such as Nanotime, Liberate, Prime Lib.
• Experience with Liberty timing models.

• Experience in SPICE simulation of CMOS circuits.
• Memory architecture fundamentals.
• STA fundamentals.
• Advanced‑node custom IP or memory characterization flows.
• Scripting and automation skills in Linux environments.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range: $ – $ USD. The range reflects the minimum and maximum target compensation for the position across all U.S. locations.

This role will be eligible for a hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.

Primary

Location:

US, California, Santa Clara. Additional Locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin.