Sr ASIC Design Verification Engineer; NetSec

Job Summary

As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next‑generation firewall products meet or exceed industry‑leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug. You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation.

• Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre‑silicon verification plans across simulation, emulation, and formal verification
• Plan and execute every aspect of simulation test plans using sophisticated coverage‑driven, constrained‑random methodologies
• Develop flows, methodologies, and infrastructure for emulation
• Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers
• Define new tools and methodologies to continuously improve quality and velocity
• Create powerful programs in Python to automate triage, coverage closure, and metrics‑driven verification

Your Experience

• BS in EE, CE, or CS required or equivalent military experience required – MSEE preferred
• Minimum 5 years experience in ASIC design verification
• Demonstrated success in taking multiple ASIC products from concept to mass production
• Expertise in System Verilog and UVM
• Defining test plans, including comprehensive adversarial testing
• Developing rich functional coverage models
• Creating powerful and scalable test benches
• Implementing sophisticated self‑checking infrastructure with reference models and scoreboards
• Developing reusable constrained‑random tests
• Debugging failures
• Closing coverage
• Experience in Networking and cyber security (preferred)
• Formal property verification
• Silicon validation – bringup, test, debug, and regression
• Creating models in Python and C/C++ and writing driver code in C
• Skilled in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing
• Demonstrated ownership and independence in planning, debugging complex failures, closing metrics‑driven tasks, driving vendors, and reporting status
• Strong leadership, collaboration, and communication skills

The compensation offered for this position will depend on qualifications, experience, and work location. The starting base salary (for non‑sales roles) or base salary + commission target (for sales/com‑missioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here ().

Palo Alto Networks is an equal opportunity employer. We celebrate diversity and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

All your information will be kept confidential according to EEO guidelines.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accomm

Is role eligible for Immigration Sponsorship? No. We will not sponsor applicants for work visas for this position.