Senior Manager, Quality Engineering

Sr ASIC Design Verification Engineer (Net Sec) – Santa Clara, California, United States. : JR-018862.

As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry‑leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug across simulation, emulation, formal verification, and silicon validation.

• Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre‑silicon verification plans across simulation, emulation, and formal verification.
• Plan and execute simulation test plans using sophisticated coverage‑driven, constrained‑random methodologies.
• Develop flows, methodologies, and infrastructure for emulation.
• Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers.
• Define new tools and methodologies to continuously improve quality and velocity.
• Create powerful programs in Python to automate triage, coverage closure, and metrics‑driven verification.

Required:

• BS in EE, CE, or CS (or equivalent military experience). MSEE preferred.
• Minimum 5 years of experience in ASIC Design Verification.
• Expertise in System Verilog and UVM.
• Mandatory experience: defining test plans with comprehensive adversarial testing, developing rich functional coverage models, creating scalable test benches, implementing self‑checking infrastructure, developing reusable constrained‑random tests, debugging failures, and closing coverage.

Preferred:

• Networking and cyber security.
• Formal property verification.
• Silicon validation – bringup, test, debug, and regression.
• Experience creating models in Python and C/C++.
• Writing driver code in
  
  C.
• Programming in Python, Perl, and UNIX shell for verification task automation.
• Demonstrated ownership, independence, leadership, collaboration, and communication skills.

The compensation offered for this position will depend on qualifications, experience, and work location. Candidates receiving an offer at the posted level will receive a base salary (non‑sales roles) or base salary plus commission target (sales/com‑missioned roles) within the annual range listed below. The offer may include restricted stock units and a bonus. Employee benefits description can be found on the company website.

We offer a range of employee benefits. We are committed to providing reasonable accommodations for qualified individuals with a disability.

Palo Alto Networks is an equal‑opportunity employer. All applicable information will be kept confidential according to EEO guidelines.

Office‑based employees are expected to work from the office four days per week, with one day remote. Flexibility may apply.