×
Register Here to Apply for Jobs or Post Jobs. X

CPU Physical Design - Low Power Signoff Engineer at Qualcomm Santa Clara, CA

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Itlearn360
Full Time position
Listed on 2026-06-21
Job specializations:
  • Engineering
    Hardware Engineer, Electronics Engineer, Test Engineer, Electrical Engineering
Salary/Wage Range or Industry Benchmark: 148300 - 222500 USD Yearly USD 148300.00 222500.00 YEAR
Job Description & How to Apply Below

Overview

CPU Physical Design - Low Power Signoff Engineer – leading CPU design efforts in Qualcomm’s CPU Engineering group in Santa Clara, CA.

Responsibilities
  • Complete ownership of conformal low power and formal verification signoff for hierarchical and flat CPU subsystems on latest technology nodes.
  • Handle CLP and FV signoff from synthesis to PNR exit.
  • Perform signoff activities including STA, power analysis, low‑power verification, PV, and related tasks.
  • Collaborate with cross‑functional teams to validate constraints, verification, STA, and physical design issues.
  • Work independently from RTL to GDSII implementation, managing block or chip level physical design, STA, and PDN activities.
  • Use low‑power flow techniques such as power gating, multi‑Vt flow, and power supply management.
  • Apply circuit‑level comprehension of critical paths, DFM, leakage power, and signal integrity.
  • Develop Tcl/Perl scripts and support technical deliveries with a small team of engineers.
Qualifications
  • 2–10 years of experience in physical design and timing signoff for high‑speed cores.
  • Experience with high‑frequency design convergence, PPA targets, and PDN methodology.
  • Master’s or Bachelor’s degree in Electrical/Electronics/Computer Engineering or related field with at least 2+ years of IC design experience.
  • Strong background in block or chip level physical design, STA, and PDN activities.
  • Proficiency in GDSII implementation, PNR flow, CLP/FV runs in 4nm/5nm/7nm/10nm nodes.
  • Hands‑on experience with LEC/CLP flows, synthesis, floor planning, PNR, and STA.
  • Knowledge of placement/clock‑tree synthesis optimization, Unix/Linux, Perl/TCL scripting.
  • 2+ years of hardware engineering experience or related work experience.
  • Good problem‑solving skills and quick learning ability.
Pay Range

$ – $ (base salary). Salary is only one component of total compensation; additional benefits include discretionary bonus, RSU grants, and a comprehensive benefits package.

EEO Statement

Qualcomm is an equal‑opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.

#J-18808-Ljbffr
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
 
 
 
Search for further Jobs Here:
(Try combinations for better Results! Or enter less keywords for broader Results)
Location
Increase/decrease your Search Radius (miles)
0
200
Filters
Education Level
Experience Level (years)
Posted in last:
Salary