Senior Signal Integrity Engineer – LPU Packaging

NVIDIA is looking for a Senior Signal Integrity Engineer to join our Packaging and Systems team!

• Lead signal integrity design and analysis for high‑speed Ser Des channels across die, package, board, connector, socket, and cable interfaces.
• Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi‑die integration, with strong focus on channel loss, discontinuities, return‑path behavior, and crosstalk.
• Build and optimize chip‑package‑board co‑simulation methodologies for next‑generation HPC and data center systems.
• Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures.
• Perform pre‑layout and post‑layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met.
• Correlate simulation with lab measurements using TDR, VNA, oscilloscope, and related measurement techniques to improve model accuracy and sign‑off confidence.
• Work closely with ASIC, package, board, mechanical, thermal, and validation teams to co‑optimize electrical performance across the full product stack.
• Support interface bring‑up, debug, and margin analysis, and help translate correlation learnings into improved design methods and reusable flows.
• Automate analysis, data processing, and visualization to improve productivity and scale SI methodology across multiple programs.

• BS, MS, or PhD in Electrical Engineering or equivalent experience.
• 8+ years of industry experience in signal integrity, high‑speed interconnect design, or related hardware development roles.
• Strong background in electromagnetics, transmission line theory, channel modeling, and high‑speed serial link behavior.
• Proven experience with high‑speed Ser Des design and analysis for advanced packaging and/or large‑scale system applications.
• Hands‑on experience with industry‑standard SI tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, or equivalent.
• Experience building and using channel models, S‑parameters, IBIS‑AMI based flows, and time/frequency‑domain analysis techniques.
• Strong understanding of NRZ and PAM4 signaling, equalization techniques, jitter/noise mechanisms, and end‑to‑end channel budgets.
• Experience with simulation‑to‑measurement correlation and lab‑based model validation using VNA, TDR, and high‑speed scope measurements.
• Ability to work effectively across cross‑functional teams and drive technical decisions in a fast‑moving product environment.
• Experience with package and system SI for PCIe, CXL, NVLink, Ethernet, or other high‑speed compute and networking interfaces.
• Deep knowledge of advanced packaging structures, substrate technologies, and chip‑package‑board co‑design.
• Background in SI design for data center, AI infrastructure, or HPC platforms.
• Experience improving SI sign‑off methodology, building reusable automation flows, or driving design rule development.
• Familiarity with mixed‑domain tradeoffs across SI, PI, thermal, mechanical, and manufacturability considerations.
• Ways to stand out from the crowd.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD – 264,500 USD for Level4, and 196,000 USD – 310,500 USD for Level
5. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.