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USD| Eng - Process Engineer - Intermediate

Job in Santa Clara, Santa Clara County, California, 95054, USA
Listing for: Artech LLC
Full Time position
Listed on 2026-07-01
Job specializations:
  • Engineering
    Quality Engineering, Electronics Engineer, Electrical Engineering, Process Engineer
Salary/Wage Range or Industry Benchmark: 44.44 - 53.33 USD Hourly USD 44.44 53.33 HOUR
Job Description & How to Apply Below
Position: USA|USD| Eng - Process Engineer - Intermediate

Position Details:

Job title:
Eng - Process Engineer

Duration: 12
-month contract

Work Location:

Santa Clara, CA

Pay rate:$44.44 - $53.33/hr. on W2.
Job : #26-18903


Experience:

1-2 Years

Key Responsibilities

· Design, collect data, analyze and compile reports on process engineering experiments for defect reduction, within safety guidelines

· Troubleshoot defect problems, perform Root Cause Analysis and resolve moderately difficult process engineering issues

· Implement new technology, products and analytical instrumentation to support the defect study

· Design the failure analysis (FA) DOE for the key defect critical components to troubleshoot the wafer defect issue on the key R&D programs and major customer escalations

· Perform the FA, collect and analyze the data within safety guidelines

· Communicate the FA observation and recommend the solution path in defect troubleshooting

· Measure the wafer defect/film properties, organize data/reports for review in supporting the defectivity improvement by SEM/FIB

· Prepare wafers for experimentation, include cleaning, loading wafers. Prepare klarf files. Evaluate and recommend performance of process system.

· Operate scanning electron microscope (SEM) for top view or critical dimension and energy dispersive spectroscopy (EDS) analysis / imaging pending on job assignment, identify all of patterns of interest, understand image quality requirement and sample/beam interaction to determine optimized condition.

· Prepare samples for Focused Ion Beam (FIB) lamella making by utilizing Zeta Marking tool and optimize sample prep procedure and conditions, identify cutting location based on pattern instructions.

· Operate and check performance of equipment to perform sample prep process, under limited supervision

· Understand the Scanning Electron Microscope (SEM) and Focused Ion Beam (FIB) principle.

· Operate Focused Ion Beam (FIB) for making TEM lamella pending on job assignment, identify all of patterns of interest, understand lamella quality requirement and sample/beam interaction to determine optimized conditions.

· Perform SEM/FIB system software alignment functions. Perform routine maintenance procedures, flash, plasma clean etc.

· Perform routine shut down procedure. Identify problem put tool down and call for service.

· Coordinates instrument repair and maintenance. Coordinates with engineering on wafer evaluations.

· Orders equipment and supplies, and coordinates with vendors and purchasing.

· Orders equipment and supplies, and coordinates with vendors and purchasing.

· Coordinates with engineering on wafer evaluations. Sets up equipment for experiments.

· Perform routine shut down procedure. Identify problem put tool down and call for service.

· Report and communicate the wafer defect analysis result, recommend the solution path for wafer defect troubleshooting on key R&D programs

· Interact with vendors/suppliers to evaluate/troubleshoot the latest defect metrology tools (SEM, EDX, FIB, Wafer scribing)

· Develop and publish best known method (BKM) procedures including, sample prep, scanning electron microscope (SEM) conditions, and special sample handling.

· Generate internal documentation for products, presentations and technical reports

· Provide trainings for junior engineers for wafer preparation/analysis on defect metrology tools

· Contribute and manage the Metrology tool (Zeta/SEMVision) operation

· Interface with requestors, understand their detail requirement, and communicate on results;

· Help lab on monitoring wafer in process (WIP) and maintaining quality, turnaround time, and throughput.

· Define and forecast the defect metrology tool requirement to support N+ defect requirement

· Host the defect knowledge sharing forum, internal workshop/conference

Regards,
Lekhana Yathiraj
Senior Technical Recruiter
Office:
Artech Information Systems LLC
360 Mt. Kemble Avenue., Suite 2000, Morristown, NJ 07960
Email: , Website:
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