Product Development Engineer - Scan Diagnostics

Overview

As a Product Development Engineer – Scan Diagnostics, you will play a core role in shaping Intel's product innovation and manufacturing excellence. Your efforts will be pivotal in transforming cutting‑edge integrated circuits from design feasibility to high‑volume production. This role offers exceptional learning and growth opportunities, providing broad exposure to the entire semiconductor product lifecycle, from initial definition to HVM. By collaborating with cross‑functional teams, you will influence product design, ensure seamless production ramp‑up, and directly contribute to delivering world‑class solutions to Intel's customers.

You'll engage in advanced diagnostic techniques for fault identification and yield improvement, collaborating with stakeholders across the company and its supplier ecosystem.

• Create, enable, and support Scan/Chain diagnosis infrastructure and processes for Intel's HVM products.
• Support fail‑based and volume diagnostic analysis, and yield analysis requests to drive continuous yield improvement.
• Support CAD infrastructure and computational resources for diagnostics across all HVM product lines.
• Develop and optimize tools, methods, and flows for design for test (DFT), diagnostics, and yield analysis.
• Collaborate with external vendors and internal teams to establish standard industry practices for diagnostics and yield analysis.
• Maintain relationships with electronic design automation (EDA) vendors to access the latest tools and methodologies.
• Facilitate knowledge transfer to ensure yield management and failure analysis team members are updated with the latest methodologies and tools.
• Define and monitor DFX quality metrics (coverage, test cost, and debuggability) from development to production ramp‑up.
• Work closely with design and new product introduction (NPI) teams to ensure diagnostic readiness for new products.

• Bachelor's degree in engineering or related field; master's degree or Ph.D. preferred.
• 4+ years of experience in DFT, Scan Diagnostics enablement, post‑Si diagnostics debug, yield analysis, and/or EDA tools.
• Proficiency in at least one of the following scripting languages:
  Python, TCL, C‑Shell, or PERL.
• Strong communication and teamwork skills.

• Experience with Siemens's Tessent Test and Yield Analysis tools or similar.
• Experience with Synopsys's Yield Explorer or similar tools.
• Experience with SOC / IP DFT control architecture (e.g., JTAG, IJTAG, IEEE 1500).
• Experience in custom and/or ASIC circuit design.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual salary range for U.S. positions: $ – $ USD.

Job Type: Experienced Hire

Shift: Shift 1 (United States).
Primary

Location:

US, California, Santa Clara.
Additional Locations: US, Arizona, Phoenix; US, Oregon, Hillsboro.

The Corporate Planning Group (CPG) is the strategic heartbeat of Intel, acting as a catalyst for innovation and transformation, guiding the company toward achieving its vision and maintaining a competitive edge in the marketplace.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.