Collateral Device Engineer

** Job Details:*
* *
* Job Description:

*
* ** About the Role*
* Are you a passionate device technologist ready to shape the future of semiconductor manufacturing? Join Intel's Manufacturing Development and Customer Engineering (MDCE) organization, where cutting-edge technology meets real-world scalability. In this role, you will sit at the intersection of innovation and execution, playing a critical part in bridging advanced technology development with practical, high-volume manufacturing solutions. If you thrive in a fast-paced, collaborative environment and are driven to solve complex challenges that impact global technology markets, this is the opportunity for you.

** About the Organization*
* The Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. The MDCE Device organization is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development.

** Position Overview*
* As a Collateral Device Engineer, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, managing OPC/Mask requests, and overseeing design rules and waivers for technologies currently in large-volume manufacturing. This role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets, including:

+ High-Performance Compute

+ Mobile

+ Mixed Signal

+ Memory Controllers

+ Diverse emerging applications

** Key Responsibilities*
* + Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring

+ Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements

+ Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications

+ Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing

+ Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities

+ Drive the development of standardized test chip methodologies and scribe line layouts compatible with Intel's existing manufacturing processes and platforms

+ Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability

+ Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers

+ Stay current with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies

*
* Qualifications:

*
* ** Minimum Qualifications*
* + Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with a focus on test chip design and device collateral development

Experience in the following:

+ CMOS semiconductor device physics and test chip design for advanced transistor device architecture

+ Scribe line layout design and process monitoring structure development

+ Design rule development, validation, and waiver management processes

+ DTCO skills, including SRAM, Standard Cells, and ability to serve as the key interface and bridge between Process Integration, Yield, Device, and Design teams

** Preferred Qualifications*
* + Ph.D. in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development

+ Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub-3nm GAA FETs

Experience in the following:

+ Design Rule Checker (DRC) development and physical verification flows

+ Experience in a…