ASIC DFT STA Engineer

Your Impact

You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips.

You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

• Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.
• Check timing for unconstrained endpoints, no clock, etc.
• Your role may include SDC validation, CDC check, and SDC flow development.
• Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.

• Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience.
• Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development.
• Prior working experience in timing constraint development and verification.
• Prior programming experience with at least 2 or more of the following scripting languages:
  Perl, TCL, Python, or Makefile.

• Masters degree + 10 years of relevant experience.
• Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints.
• Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.
• Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime.
• Prior working experience with synthesis tools:
  Synopsys Fusion/design Compiler.
• Prior working experience with Tessent tool like DFT insertion in RTL.

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The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined…