DFT Timing Engineer – Chip-Level Closure & Automation
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-07-14
Listing for:
Segment (Twilio)
Full Time
position Listed on 2026-07-14
Job specializations:
-
Engineering
Electronics Engineer, Automation & Mechatronics Engineer, Hardware Engineer
Job Description & How to Apply Below
NVIDIA is seeking a DFT-Timing Engineer in Santa Clara, CA to drive timing analysis and closure for DFT logic on NVIDIA chips at block, cluster, and full-chip levels. You will collaborate with PD, DFX, Clocks and other teams to develop timing-closure strategies and create timing constraints for custom DFT designs.
You will implement ECOs and continuously improve workflows through automation and standardization.
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