Lead DFT Methodology Engineer SoC Test & Verification
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-07-18
Listing for:
Segment (Twilio)
Full Time
position Listed on 2026-07-18
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
NVIDIA is seeking a DFT Methodology Engineer to drive advanced test access mechanisms, I1149.1/I1500/I1687, memory BIST, and DFX security for multi-million gate SoCs in Santa Clara, CA. You will partner with RTL, timing, physical design, and software teams to shape next-gen products and validate designs through silicon bring-up.
The role requires a Master’s in EE or related field and 10+ years of hands-on experience in DFT, SoC architecture, RTL design, and verification.
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