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SOC Verification and Methodology Engineer - SCL

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Qualcomm
Full Time position
Listed on 2026-07-21
Job specializations:
  • Engineering
    Test Engineer
Salary/Wage Range or Industry Benchmark: 153200 - 229800 USD Yearly USD 153200.00 229800.00 YEAR
Job Description & How to Apply Below

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. This is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5

Gs potential into world‑changing technologies and products. This is the Invention Age – and this is where you come in.

We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design, and verification fundamentals and a drive to innovate new solutions. This position under Qualcomm's Global SOC organization offers the rare opportunity to have real impact in shaping 5G product lines ranging from low‑power Snapdragon chips to the growing field of Machine Learning (AI/ML) and to Autonomous driving.

Job Overview

Qualcomm SoC HW team is responsible for developing and delivering best‑in‑class premium tier smartphone SoC solutions which set benchmarks across the industry. As an SOC Verification and Methodology Engineer, you will ensure the quality and functionality of System‑on‑Chip (SOC) designs through comprehensive verification processes. You will develop and implement verification methodologies, create test plans, and execute verification tests to identify and resolve design issues, including system‑level integration validation.

Key Responsibilities
  • Develop Verification Plans: understand design specifications and define verification scope. Develop detailed test plans and verification infrastructure.
  • Execute Verification Tests: implement and run verification test cases, debug complex issues, and analyze System Verilog assertions and coverage (code, toggle, functional).
  • Collaborate with Teams: work closely with architects, designers, and pre‑ and post‑silicon verification teams to accomplish tasks.
  • Innovate Solutions: develop innovative solutions to verification challenges with minimal guidance, ramp up on new verification tools and methodologies, and explore DV techniques to continuously improve test‑bench quality and efficiency.
  • Adhere to Standards: maintain quality standards and best practices in test and verification processes.
  • Engage with global design, verification, silicon, and architecture teams to achieve all project goals and demonstrate strong communication skills.
Qualifications
  • Bachelor’s degree in Science, Engineering, or related field.
  • Minimum 2+ years of design verification experience. Senior positions offered to candidates with proven expertise.
  • Good understanding of System Verilog/UVM based verification skills & experience with assertion & coverage‑based methodology.
  • Experience handling verification from test planning to tape‑out for large‑size hardware design.
Preferred Qualifications
  • Master’s degree in Science, Engineering, or related field.
  • 5+ years industry experience with knowledge of SOC architecture, CPU architecture (ARM knowledge helpful), DSP, AMBA Bus, DDR, GPU, Multimedia, etc.
  • Exposure to ARM SBSA (Server Base System Architecture).
  • Experience with heterogeneous multi‑die system verification.
  • Experience with D2D interfaces (e.g., UCIe, CXL) verification.
  • Experience with pre‑silicon emulation platform‑based verification.
  • Knowledge of power design, architecture, and verification requirements.
  • Passion for debugging and strong problem‑solving abilities.
  • Experience with scripting languages such as Perl, Python (plus).
  • Assertion coding and convergence on formal tools (plus).
Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Pay range and Other Compensation & Benefits

$ - $. The above pay scale reflects the broad minimum to maximum pay range for this job code at the posted location. Salary is only one component of total compensation. A competitive annual discretionary bonus program and opportunity for annual RSU grants are also offered.

EEO Employer

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. Reasonable accommodations can be requested at disabili or by phone. Qualcomm also commits to keeping its workplace accessible for individuals with disabilities.

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