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Senior ASIC Timing Engineer, DFT

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: NVIDIA
Full Time position
Listed on 2026-07-22
Job specializations:
  • Engineering
    Hardware Engineer, Electronics Engineer, Test Engineer, Automation & Mechatronics Engineer
Salary/Wage Range or Industry Benchmark: 168000 - 264500 USD Yearly USD 168000.00 264500.00 YEAR
Job Description & How to Apply Below

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing, where our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world.

Doing what’s never been done before takes vision, innovation, and the world’s best talent.

We’re looking for a motivated DFT‑Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today!

What You’ll Be Doing
  • Drive timing analysis and closure for DFT logic on all NVIDIA chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full‑chip).
  • Work with PD, DFX, Clocks and other teams to develop timing closure strategy, create timing constraints for custom DFT designs, drive timing and power convergence, and implement ECOs.
  • Continuously improve workflows and designs by introducing more automation, resilience, and standardization.
What We Need To See
  • BS (or equivalent) in Electrical or Computer Engineering with 5+ years’ experience, or MS (or equivalent) with 2+ years’ experience.
  • Hands‑on experience in Static Timing Analysis (STA) and driving timing convergence at full‑chip/sub‑chip level in advanced technology nodes.
  • Expertise in analysis and fixing of timing paths through ECOs.
  • Expertise in developing timing constraints.
  • In‑depth knowledge of industry standard timing convergence tools.
Ways To Stand Out From The Crowd
  • Understanding of DFT logic and experience with DFT timing closure for various modes (e.g., scan, iJTAG).
  • Background in domain‑specific STA and timing convergence, such as Serdes, Processor, IO, SMVA, etc.
  • Experience in methodology and/or workflow development.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $136,000 – $218,500 for Level 3, and $168,000 – $264,500 for Level 4. You will also be eligible for equity and benefits.

NVIDIA uses AI tools in its recruiting processes. This posting is for an existing vacancy.

NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.

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Position Requirements
10+ Years work experience
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