ASIC Floorplan Design Engineer - College Grad

What you will be doing:

• Working with architects, design leads, physical design leads and package leads, you will develop and craft and optimize floor plans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
• You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
• A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
• Experience in Verilog, System Verilog or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and ability and desire to work as a great teammate should be displayed in your interview.
• Python, Perl and C/C++ programming language experience.

• Experience in driving development of large scale ASIC floorplan is a huge plus.

Compensation:
The base salary range is $100,000 - $166,750 for Level 1, and $116,000 - $189,750 for Level 2. You will also be eligible for equity and benefits.

Applications will be accepted until July3, 2026.

We are committed to fostering an inclusive work environment and are an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.